Method and system for iteratively testing and repairing an array of memory cells
US8615688B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2013 |
| Grant date | Dec 24, 2013 |
| Priority date | — |
| Expiry date | Apr 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes an array of memory cells and a repair module. Multiple memory cells in the array are redundant to other memory cells in the array. The repair module iteratively tests the array. During the iterative testing of the array, the repair module, during each test of the array, (i) identifies one or more defective memory cells in the array, if any, and (ii) in response to one or more defective memory cells being identified during the test, respectively replaces the one or more defective memory cells with one or more memory cells that are redundant to other memory cells in the array. The repair module performs the iterative testing of the array until (i) the repair module does not detect a defective memory cell or (ii) no memory cells of the memory cells that are redundant remain available for replacement of a defective memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.