Integrated circuits and methods for forming the integrated circuits
US8617986B2 · kind B2 · utility
4Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2010 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Oct 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/04941
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an integrated circuit includes forming a first dielectric layer over a gate electrode of a transistor. An etch-stop layer is formed over the first dielectric layer. An opening is formed through the first dielectric layer and the etch-stop layer, exposing a source/drain (S/D) region of the transistor. A metal layer is formed in the opening, contacting the S/D region of the transistor. The metal layer has a surface that is at least partially substantially level with a first top surface of the etch-stop layer. A damascene structure is formed and coupled with the metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.