Liner property improvement
US8617989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2012 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Jun 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a dielectric liner layer on a semiconductor substrate are described. The method may include flowing a phosphorus-containing precursor with a silicon-containing precursor and an oxygen-containing precursor over the substrate to deposit a dielectric material. The dielectric material may be deposited along a field region and within at least one via on the substrate having a depth of at least 1 μm. The method may also include forming a liner layer within the via with the dielectric material. The liner may include a silicon oxide doped with phosphorus, and the thickness of the liner layer at an upper portion of the via sidewall may be less than about 5 times the thickness of the liner layer at a lower portion of the via sidewall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.