Forming functionalized carrier structures with coreless packages
US8618652B2 · kind B2 · utility
25Cited by
57References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2010 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Jul 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/185
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.