Pattern layout in semiconductor device
US8618665B2 · kind B2 · utility
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1References
13Claims
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Assignee
Inventors
Key dates
| Filing date | Sep 16, 2011 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Feb 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor device having a pattern layout includes a first interconnect pattern and a contact pad. The first interconnect pattern includes lines and spaces which are alternately aligned in a first direction with a predetermined pitch. The contact pad is arranged between the lines in the first interconnect pattern and has a width that is triple the predetermined pitch. An interval between the line in the first interconnect pattern and the contact pad is the predetermined pitch, and the predetermined pitch is 100 nm or below.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.