Source series terminated driver circuit with programmable output resistance, amplitude reduction, and equalization
US8618833B1 · kind B1 · utility
6Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2012 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Jun 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018585
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A source-series terminated (‘SST’) driver circuit that includes: one or more data signal inputs; one or more control signal inputs; a driver output; and a plurality of driver cells, the driver cells coupled in parallel to one another, outputs of the driver cells coupled together to form the driver output of the SST driver circuit, where output resistance of the SST driver circuit varies in dependence upon activation of one or more of the parallel driver cells, activation of each driver cell controlled by control signals received at the control signal inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.