System and method of transistor switch biasing in a high power semiconductor switch
US8618860B2 · kind B2 · utility
1Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | Dec 10, 2012 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Dec 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and method are provided for switching in a semiconductor based high power switch. Complementary p-type based transistors are utilized along insertion loss insensitive paths allowing biasing voltages to alternate between supply and ground, allowing for negative voltage supplies and blocking capacitors to be dispensed with, while improving performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.