Semiconductor memory devices
US8619490B2 · kind B2 · utility
175Cited by
4References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2011 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Dec 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory devices include a first storage layer and a second storage layer, each of which includes at least one array, and a control layer for controlling access to the first storage layer and the second storage layer so as to write data to or read data from the array included in the first storage layer or the second storage layer in correspondence to a control signal. A memory capacity of the array included in the first storage layer is different from a memory capacity of the array included in the second storage layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.