Variable impedance memory element structures, methods of manufacture, and memory devices containing the same

US8624219B1 · kind B1 · utility

Assignee

• Adesto Technologies Corporation · US

Inventors

• John Ross Jameson · Burlingame, US
• Antonio R. Gallo · Colorado Springs, US
• Foroozan Sarah Koushan · San Jose, US
• Michael A. Van Buskirk · Saratoga, US

Key dates

• Filing date: Apr 12, 2012
• Grant date: Jan 7, 2014
• Expiry date: Apr 12, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/821

Abstract

A memory device can include at least one cathode formed in first opening of a first insulating layer; at least one anode formed in a second opening of second insulating layer, the second insulating layer being a different vertical layer than the first insulating layer; and a memory layer comprising an ion conductor layer extending laterally between the at least one anode and cathode on the first insulating layer, the ion conductor layer having a thickness in the vertical direction less than a depth of the first opening.