High electron mobility transistor including an embedded flourine region
US8624296B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2012 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Aug 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. The second III-V compound layer has a top surface. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. The fluorine region has a top surface lower than the top surface of the second III-V compound layer. A gate dielectric layer is disposed under at least a portion of the gate electrode and over the fluorine region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.