Multi-layer circuit substrate fabrication and design methods providing improved transmission line integrity and increased routing density
US8624297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2009 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Oct 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/0969
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.