Contact integration for three-dimensional stacking semiconductor devices

US8624300B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Sanh D. Tang · Boise, US
• John K. Zahurak · Eagle, US
• Shane J. Trapp · Boise, US
• Krishna K. Parat · Palo Alto, US

Key dates

• Filing date: Dec 16, 2010
• Grant date: Jan 7, 2014
• Expiry date: Aug 29, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/01

Abstract

Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.