Shane J. Trapp
21Patents
6h-index
30Co-inventors
69Inventor score
Filing activity: Aug 31, 2000 → Sep 4, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6451705B1 | Self-aligned PECVD etch mask | Emerging Cross-Sectional Technologies | 34 | Expired |
| US7153779B2 | Method to eliminate striations and surface roughness caused by dry etch | Electricity | 33 | Expired |
| US6569774B1 | Method to eliminate striations and surface roughness caused by dry etch | Electricity | 31 | Expired |
| US6630410B2 | Self-aligned PECVD etch mask | Emerging Cross-Sectional Technologies | 27 | Expired |
| US6897120B2 | Method of forming integrated circuitry and method of forming shallow trench isolation in a semiconductor substrate | Electricity | 22 | Expired |
| US8624300B2 | Contact integration for three-dimensional stacking semiconductor devices | Electricity | 12 | Active |
| US7202171B2 | Method for forming a contact opening in a semiconductor device | Electricity | 6 | Expired |
| US7344975B2 | Method to reduce charge buildup during high aspect ratio contact etch | Emerging Cross-Sectional Technologies | 4 | Expired |
| US8889559B2 | Methods of forming a pattern on a substrate | Emerging Cross-Sectional Technologies | 4 | Active |
| US6806197B2 | Method of forming integrated circuitry, and method of forming a contact opening | Emerging Cross-Sectional Technologies | 2 | Expired |
| US9679852B2 | Semiconductor constructions | Electricity | 2 | Active |
| US8673787B2 | Method to reduce charge buildup during high aspect ratio contact etch | Emerging Cross-Sectional Technologies | 2 | Active |
| US7985692B2 | Method to reduce charge buildup during high aspect ratio contact etch | Emerging Cross-Sectional Technologies | 1 | Active |
| US8999852B2 | Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice pattern from an oblique lattice pattern, and methods of forming a pattern on a substrate | Electricity | 1 | Active |
| US9984977B2 | Semiconductor constructions | Electricity | 1 | Active |
| US8889558B2 | Methods of forming a pattern on a substrate | Electricity | 1 | Active |
| US9741580B2 | Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice pattern from an oblique lattice pattern, and methods of forming a pattern on a substrate | Electricity | 0 | Active |
| US11672118B2 | Electronic devices comprising adjoining oxide materials and related systems | Electricity | 0 | Active |
| US7291895B2 | Integrated circuitry | Emerging Cross-Sectional Technologies | 0 | Expired |
| US7419913B2 | Methods of forming openings into dielectric material | Electricity | 0 | Expired |
| US10930548B2 | Methods of forming an apparatus for making semiconductor dieves | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.