Patent · US Active

Semiconductor device and method of manufacturing the same

US8624325B2 · kind B2 · utility

1Cited by
0References
6Claims
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Assignee

Inventors

Key dates

Filing dateJun 23, 2010
Grant dateJan 7, 2014
Priority date
Expiry dateJun 23, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/0184

Abstract

The present invention provides a semiconductor device, comprising: a semiconductor substrate having a first region and a second region; a first gate structure belong to a PMOS device on the first region; a second gate structure belong to an nMOS device on the second region; a multiple-layer first sidewall spacer on sidewalls of the first gate structure, wherein a layer of the multiple-layer first sidewall spacer adjacent to the first gat structure is an oxide layer; a multiple-layer second sidewall spacer on sidewalls of the second gate structure, wherein a layer of the multiple layers of second sidewall spacer adjacent to the first gat structure is a nitride layer. Application of the present invention may alleviate the oxygen vacancy in a high-k gate dielectric in a pMOS device, and further avoid the problem of EOT growth of an nMOS device during the high-temperature thermal treatment process, and therefore effectively improve the overall performance of the high-k gate dielectric CMOS device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.