Package carrier and manufacturing method thereof
US8624388B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 21, 2011 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Sep 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a manufacturing method of a package carrier, a substrate including a first metal layer, a second metal layer having a top surface and a bottom surface opposite to each other, and an insulating layer between the first and second metal layers is provided. The second metal layer has a greater thickness than the first metal layer. A first opening passing through the first metal layer and the insulating layer and exposing a portion of the top surface of the second metal layer is formed. The first metal layer is patterned to form a patterned conductive layer. Second openings are formed on the bottom surface of the second metal layer. The second metal layer is divided into thermal conductive blocks by the second openings that do not connect the first opening. A surface passivation layer is formed on the patterned conductive layer and the exposed portion of the top surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.