Flexible sequence design architecture for solid state memory controller
US8626995B1 · kind B1 · utility
2Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Aug 27, 2012 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Aug 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0246
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some implementations, a method includes receiving commands from a host device, sending the commands to one or more flash memory devices, receiving information associated with at least one of the commands from the one or more flash memory devices, and selectively sending the information to the host device based on whether one or more parameters in the at least one command include a request to receive the information from the one or more flash memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.