Store data forwarding with no memory model restrictions
US8627047B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2008 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Sep 9, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3834
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load request, where the load request may require at least one updated completed block of data: determining if store forwarding is appropriate for the load request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.