Verification for functional independence of logic designs that use redundant representation
US8627248B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2012 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Jul 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer-implemented techniques are disclosed for verifying functional independence of logic designs that make use of redundant representations. Initially, the design of a logic component is obtained. Two representations of the component are computed, one in redundant form and another in non-redundant form. A randomness factor based on a time-varying value is injected into the second representation. The value from the second form is then constrained to the context of the logic component within a digital system. It is then possible to analyze the component using the first deterministic representation and the constrained second representation. This analysis allows verification of the component with downstream logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.