Method and system for high speed and low memory footprint static timing analysis
US8627250B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2013 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Jul 2, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a method and system for performing Static Timing Analysis on SoC (System on a Chip) designs. The invention solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention provides for slicing a design into levels, further decomposing each level into gates, and the multi-threaded processing of gates so that the solution of large design analysis is generated significantly faster than current approaches. Further, the invention provides that only one level exists in the RAM at any time. Once the arrival time on the level is computed, the data is saved to disk immediately. Because the memory footprint is sub-linear to the size of the design, entire system-on-a chip designs may be run on inexpensive, off-the-shelf hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.