Systems and methods of automatically detecting failure patterns for semiconductor wafer fabrication processes
US8627251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2012 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | May 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.