Patent · US Active

Junction leakage reduction through implantation

US8629013B2 · kind B2 · utility

3Cited by

1References

18Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Chun-Feng Nieh · Hsinchu, TW
Chung-Yi Yu · Baoshan, TW
Hung-Ta Lin · Hsinchu, TW

Key dates

Filing date	Oct 14, 2011
Grant date	Jan 14, 2014
Priority date	—
Expiry date	Dec 6, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/85
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Provided is a method of fabricating a semiconductor device. The method includes forming a first III-V family layer over a substrate. The first III-V family layer includes a surface having a first surface morphology. The method includes performing an ion implantation process to the first III-V family layer through the surface. The ion implantation process changes the first surface morphology into a second surface morphology. After the ion implantation process is performed, the method includes forming a second III-V family layer over the first III-V family layer. The second III-V family layer has a material composition different from that of the first III-V family layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.