Integration scheme for an NMOS metal gate
US8629021B2 · kind B2 · utility
0Cited by
5References
17Claims
0Family size
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Key dates
| Filing date | Nov 2, 2007 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Jul 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.