Semiconductor device and method for fabricating semiconductor device
US8629025B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2012 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Apr 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.