Methods of forming integrated circuit chips having vertically extended through-substrate vias therein
US8629059B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2010 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Feb 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.