Method of and system for time-division based parallelization of graphics processing units (GPUs) employing a hardware hub with router interfaced between the CPU and the GPUs for the transfer of geometric data and graphics commands and rendered pixel data within the system
US8629877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2007 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Feb 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2200/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of dynamic load-balancing in a PC-based computing system employing a multiple GPU-based graphics pipeline architecture supporting multiple modes of GPU parallelization. During the execution of the graphics application, the stream of geometrical data and said graphics commands is analyzed, and the mode of parallelization of the GPUs during each frame, is determined using results of the analysis of the stream of geometrical data and graphics commands, and one or more policies for determining the mode of parallelization. The stream of geometrical data and graphic commands is distributed to the GPUs according to the determined mode of parallelization. During the generation of each frame, one or more of GPUs are used to process the stream of geometrical data and graphic commands, or a portion thereof, while operating in the parallelization mode, so as to generate pixel data corresponding to at least a portion of an image of 3D object. The pixel data output is transferred from one or more of the GPUs and composing a frame of pixel data, representative of the image of the 3D object. The frame of pixel data is displayed on a display surface of the PC-based computing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.