Offir Remez
17Patents
5h-index
6Co-inventors
55Inventor score
Filing activity: Nov 19, 2004 → Jun 16, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7800610B2 | PC-based computing system employing a multi-GPU graphics pipeline architecture supporting multiple modes of GPU parallelization dymamically controlled while running a graphics application | Physics | 8 | Active |
| US7800611B2 | Graphics hub subsystem for interfacing parallalized graphics processing units (GPUs) with the central processing unit (CPU) of a PC-based computing system having an CPU interface module and a PC bus | Physics | 7 | Active |
| US8629877B2 | Method of and system for time-division based parallelization of graphics processing units (GPUs) employing a hardware hub with router interfaced between the CPU and the GPUs for the transfer of geometric data and graphics commands and rendered pixel data within the system | Physics | 7 | Active |
| US7808499B2 | PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router | Physics | 7 | Active |
| US7796129B2 | Multi-GPU graphics processing subsystem for installation in a PC-based computing system having a central processing unit (CPU) and a PC bus | Physics | 6 | Active |
| US7812846B2 | PC-based computing system employing a silicon chip of monolithic construction having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operation | Physics | 5 | Active |
| US7834880B2 | Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction | Physics | 5 | Active |
| US7808504B2 | PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUS) from the same or different vendors, in a manner transparent to graphics applications | Physics | 5 | Active |
| US7796130B2 | PC-based computing system employing multiple graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware hub, and parallelized according to the object division mode of parallel operation | Physics | 4 | Active |
| US7800619B2 | Method of providing a PC-based computing system with parallel graphics processing capabilities | Physics | 4 | Active |
| US7843457B2 | PC-based computing systems employing a bridge chip having a routing unit for distributing geometrical data and graphics commands to parallelized GPU-driven pipeline cores supported on a plurality of graphics cards and said bridge chip during the running of a graphics application | Physics | 3 | Active |
| US7812845B2 | PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application | Physics | 3 | Active |
| US7812844B2 | PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallel operation during the running of a graphics application | Physics | 3 | Active |
| US9082196B2 | Application-transparent resolution control by way of command stream interception | Physics | 1 | Active |
| US8754897B2 | Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem | Physics | 0 | Active |
| US9659340B2 | Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem | Physics | 0 | Active |
| US9405586B2 | Method of dynamic load-balancing within a PC-based computing system employing a multiple GPU-based graphics pipeline architecture supporting multiple modes of GPU parallelization | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.