SRAM read and write assist apparatus
US8630132B2 · kind B2 · utility
179Cited by
1References
20Claims
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Assignee
Inventors
Key dates
| Filing date | May 31, 2011 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Jul 20, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit. The bit line voltage tracking block detects a voltage on a tracking bit line coupled to a plurality of tracking memory cells. In response to the voltage drop on the tracking bit line, the READ assist timer generates a READ assist pulse. When the READ assist pulse has a logic high state, an activated word line is pulled down to a lower voltage. Such a lower voltage helps to improve the robustness of SRAM memory circuits so as to avoid READ and WRITE failures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.