GaN high voltage HFET with passivation plus gate dielectric multilayer structure
US8633094B2 · kind B2 · utility
25Cited by
72References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2011 |
| Grant date | Jan 21, 2014 |
| Priority date | — |
| Expiry date | Apr 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.