Synchronized clock phase interpolator
US8634509B2 · kind B2 · utility
6Cited by
1References
10Claims
0Family size
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Key dates
| Filing date | Feb 15, 2012 |
| Grant date | Jan 21, 2014 |
| Priority date | — |
| Expiry date | Apr 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0025
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.