Translation of input/output addresses to memory addresses
US8635430B2 · kind B2 · utility
6Cited by
113References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2010 |
| Grant date | Jan 21, 2014 |
| Priority date | — |
| Expiry date | Apr 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.