Hardware device for processing the tasks of an algorithm in parallel
US8635620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2012 |
| Grant date | Jan 21, 2014 |
| Priority date | — |
| Expiry date | May 31, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.