Method of manufacturing chip-stacked semiconductor package
US8637350B2 · kind B2 · utility
5Cited by
0References
20Claims
0Family size
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Key dates
| Filing date | Apr 4, 2012 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Apr 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.