FinFET parasitic capacitance reduction using air gap

US8637384B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Takashi Ando · Tuckahoe, US
• Josephine B. Chang · Mahopac, US
• Sivananda K. Kanakasabapathy · Niskayuna, US
• Pranita Kulkarni · Slingerlands, US
• Theodorus E. Standaert · Clifton Park, US
• Tenko Yamashita · Schenectady, US

Key dates

• Filing date: Sep 14, 2012
• Grant date: Jan 28, 2014
• Expiry date: Sep 14, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a length and a height defining two opposing sidewalls of the gate structure and being formed such that the channel said passes through the sidewalls; forming spacers on the sidewalls; forming a layer of epitaxial silicon over the channel; removing the spacers; and forming a dielectric layer to be disposed over the gate structure and portions of the channel that are external to the gate structure such that a capacitance-reducing air gap underlies the dielectric layer and is disposed adjacent to the sidewalls of said gate structure in a region formerly occupied by the spacers.