Flip chip semiconductor assembly with variable volume solder bumps
US8637391B2 · kind B2 · utility
0Cited by
7References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 7, 2009 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Jun 15, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/20109
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.