Thermally enhanced semiconductor packages and related methods
US8637887B2 · kind B2 · utility
1Cited by
11References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 8, 2012 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | May 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/857
Abstract
A chip package having a lead frame and a molded portion. The lead frame includes a thermal pad and at least one electrode. The molded portion partially encapsulates the at least one electrode such that it is exposed on a top surface but not on a bottom surface. A bottom surface of the thermal pad is exposed for direct securement to an external heat sink. The molded portion is disposed between the at least one electrode and the heat sink to prevent a short circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.