FinFET parasitic capacitance reduction using air gap

US8637930B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Takashi Ando · Tuckahoe, US
• Josephine B. Chang · Mahopac, US
• Sivananda K. Kanakasabapathy · Niskayuna, US
• Pranita Kulkarni · Slingerlands, US
• Theodorus E. Standaert · Clifton Park, US
• Tenko Yamashita · Schenectady, US

Key dates

• Filing date: Oct 13, 2011
• Grant date: Jan 28, 2014
• Expiry date: Jan 25, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

A transistor, for example a FinFET, includes a gate structure disposed over a substrate. The gate structure has a width and also a length and a height defining two opposing sidewalls of the gate structure. The transistor further includes at least one electrically conductive channel between a source region and a drain region that passes through the sidewalls of the gate structure; a dielectric layer disposed over the gate structure and portions of the electrically conductive channel that are external to the gate structure; and an air gap underlying the dielectric layer. The air gap is disposed adjacent to the sidewalls of the gate structure and functions to reduce parasitic capacitance of the transistor. At least one method to fabricate the transistor is also disclosed.