Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width
US8638153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2012 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | May 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.