Patent · US Active

Dual port static random access memory cell

US8638592B2 · kind B2 · utility

7Cited by

5References

16Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Sayeed A. Badrudduza · Austin, US
Jack M. Higman · Austin, US
Sanjay R. Parihar · Austin, US

Key dates

Filing date	Sep 8, 2011
Grant date	Jan 28, 2014
Priority date	—
Expiry date	Mar 8, 2032

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10T29/49117
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An SRAM has at least two sets of pass transistors for coupling at least two sets of bit lines to true and complement data nodes of an SRAM cell based on the assertion of at least two word lines. The cell includes two pull up transistors and two pull down transistors coupled to the true and complement data nodes. None of the pass transistors are implemented in an active area that includes a pull up transistor or a pull down transistor of the cell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.