Vertical nonvolatile memory devices and methods of operating same
US8638611B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2012 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Feb 11, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.