Semiconductor memory device having a hierarchical bit line scheme
US8638621B2 · kind B2 · utility
3Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2012 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Apr 18, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.