Hardware description language simulator tracing and control
US8640064B1 · kind B1 · utility
7Cited by
2References
5Claims
0Family size
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Key dates
| Filing date | Jun 12, 2012 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Jun 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processing a circuit design specified in a hardware description language (HDL) can include, for each of a plurality of nets of the circuit design, creating a trace memory structure, using a processor, during compilation of the HDL circuit design. Each trace memory structure can include trace properties indicating whether tracing is active for the net. A transaction function can be generated during compilation for each net. The transaction function can be configured to invoke tracing for each net during simulation of the circuit design according to an evaluation of the trace properties for the net.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.