Capturing mutual coupling effects between an integrated circuit chip and chip package
US8640077B1 · kind B1 · utility
3Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2012 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Jul 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for capturing mutual coupling effects between an integrated circuit chip and chip package using electronic design automation (EDA) tools. Specifically, a method is provided that is implemented in a computer infrastructure for designing an integrated circuit chip. The method includes compiling process technology parameters that describe electrical behavior for a chip-package coupling and a package of the integrated circuit chip. The method also includes generating a parasitic technology file to include the compiled process technology parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.