Method of forming three dimensional integrated circuit devices using layer transfer technique
US8642416B2 · kind B2 · utility
37Cited by
322References
20Claims
0Family size
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Key dates
| Filing date | Jun 28, 2011 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Jun 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/125
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for formation of a semiconductor device including a first wafer including a first single crystal layer comprising first transistors and first alignment mark, the method including: implanting to form a doped layer within a second wafer; forming a second mono-crystalline layer on top of the first wafer by transferring at least a portion of the doped layer using layer transfer step, and completing the formation of second transistors on the second mono-crystalline layer including a step of forming a gate dielectric followed by second transistors gate formation step, wherein the second transistors are horizontally oriented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.