Semiconductor device, method for manufacturing same, and semiconductor storage device
US8643117B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2010 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Jul 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6734
Abstract
In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.