Semiconductor device using multi-phase clock signal and information processing system including the same
US8643413B2 · kind B2 · utility
1Cited by
3References
18Claims
0Family size
Inventors
Key dates
| Filing date | Aug 29, 2012 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Aug 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.