Leakage-aware keeper for semiconductor memory
US8644087B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2011 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Mar 19, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a first circuit configured to sense a leakage of a first bit line and output a first signal in response, and a second circuit configured to receive the first signal output from the first circuit and in response supply current to a second bit line for maintaining a voltage level of the second bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.