Convolution filtering in a graphics processor
US8644643B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2006 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Apr 6, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for performing convolution filtering using hardware normally available in a graphics processor are described. Convolution filtering of an arbitrary H×W grid of pixels is achieved by partitioning the grid into smaller sections, performing computation for each section, and combining the intermediate results for all sections to obtain a final result. In one design, a command to perform convolution filtering on a grid of pixels with a kernel of coefficients is received, e.g., from a graphics application. The grid is partitioned into multiple sections, where each section may be 2×2 or smaller. Multiple instructions are generated for the multiple sections, with each instruction performing convolution computation on at least one pixel in one section. Each instruction may include pixel position information and applicable kernel coefficients. Instructions to combine the intermediate results from the multiple instructions are also generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.