Upbound input/output expansion request and response processing in a PCIe architecture
US8645606B2 · kind B2 · utility
3Cited by
161References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2010 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Mar 8, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to upbound input/output expansion requests and response processing in a PCIE architecture. A first request to perform an operation on a host system is intitiated. The first request is formatted for the first protocol and includes data that is required in order to process the first request. A second request is created in response to the first request, the second request includes a header and is formatted according to the second protocol. The data required to process the first request in the header of the second request is stored, and the second request is sent to the host system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.