Patent · US Active

Combined L2 cache and L1D cache prefetcher

US8645631B2 · kind B2 · utility

2Cited by

2References

29Claims

0Family size

Assignee

VIA Technologies, Inc. · TW

Inventors

Rodney E. Hooker · Austin, US
John Michael Greer · Navan, IE

Key dates

Filing date	Feb 24, 2011
Grant date	Feb 4, 2014
Priority date	—
Expiry date	Oct 4, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/6026
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A microprocessor includes a first-level cache memory, a second-level cache memory, and a data prefetcher that detects a predominant direction and pattern of recent memory accesses presented to the second-level cache memory and prefetches cache lines into the second-level cache memory based on the predominant direction and pattern. The data prefetcher also receives from the first-level cache memory an address of a memory access received by the first-level cache memory, wherein the address implicates a cache line. The data prefetcher also determines one or more cache lines indicated by the pattern beyond the implicated cache line in the predominant direction. The data prefetcher also causes the one or more cache lines to be prefetched into the first-level cache memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.