Branch target address cache for predicting instruction decryption keys in a microprocessor that fetches and decrypts encrypted instructions
US8645714B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2011 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Dec 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A branch target address cache (BTAC) caches history information associated with branch and switch key instructions previously executed by a microprocessor. The history information includes a target address and an identifier (index into a register file) for identifying key values associated with each of the previous branch and switch key instructions. A fetch unit receives from the BTAC a prediction that the fetch unit fetched a previous branch and switch key instruction and receives the target address and identifier associated with the fetched branch and switch key instruction. The fetch unit also fetches encrypted instruction data at the associated target address and decrypts (via XOR) the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction. If the BTAC predicts correctly, a pipeline flush normally associated with the branch and switch key instruction is avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.